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Papers tagged with "Low Power"
Area - Delay - Power Efficient Carry Select Adder
In Modern VLSI Design, Arithmetic Circuits Are Fundamental Components That Directly Influence The Performance, Power Consumption, And Silicon Area Of Digital Systems. The Carry Select Adder (CSLA) Is One Of The Most Widely Used High-speed A...
EFFICIENT REVERSIBLE FOR QUANTUM COMPUTING A NOVEL 4-BIT LFSR APPROACH
Reversible Logic Gates Are Critical Components In The Field Of Quantum Computing And Low-power Digital Circuits, As They Allow For The Retrieval Of Input States From Output States Without Any Loss Of Information. This Property Ensures Minim...
DESIGN AND EVALUATION OF LOW POWER DECODER CIRCUIT USING VITERBI DECODER
This Paper Presents A New Design Of A 2 To 4 Decoder Constructed Using 3-transistor NAND Gates, Contrasting It With The Conventional 4 Transistor NAND Gate-based Technique. The Primary Aim Of This Paper Is To Exhibit Advancements In Power E...
AN EFFICIENT BCD ADDER DESIGN UTILIZING REVERSIBLE LOGIC TECHNIQUES
Reversible Logic Gates Are Pivotal Components Digital Circuit Design, Embodying The Principle Of Reversibility That Ensures Each Input State Maps Uniquely To A Distinct Output State Without Loss Of Information. Leveraging These Principles,...
FPGA IMPLEMENTATION OF LOW POWER PARALLEL MULTIPLIER
In The Fast Growing Communication Field, Requirements Of Low Power Designs Are Increasing To Reduce The Power Losses And Decrease The Thermal Losses In The Same Ratio.Multiplier Is An Arithmetic Circuit That Is Extensively Used In Common DS...
design of low-power high-gain serializer/deserializer using gdi technique
CMOS Technology Is Evolving Propose And Demonstrate A Serializer/deserializer (SerDes) Toward The Testing Of Large Scale GDI Circuits With Delay-line Clocking. A SerDes, A Pair Of A Serializer (parallel-to-serial Converter) And A Deserializ...
VLSI IMPLIMENTATION OF FULL SUBTRACTOR USING SPLIT-RAIL CHARGE RECOVERY LOGIC
CMOS Technology Is Evolving Rapidly With The Advancement In VLSI Design. The Gate Count On The Integrated Chip Is Steadily Rising Which Leads To Enhanced Power Dissipation And Heat Generation. Therefore, A New Paradigm That Can Circumvent T...
FAULT TOLERANT REVERSIBLE OF VARIOUS ADDERS DESIGN USING DIFFERENT LOW POWER CONSUMPTION TECHNIQUES
GDI Technique Allows Minimization Of Area And Power Consumption Of Digital Circuits. The Reversible Gate Preserves Same Parity Between Output And Input Vectors Is Called Fault Tolerant But The Dimension Should Be 3. In This Design, Peres Ga...
DESIGN AND IMPLEMENTATION OF LOW POWER SEQUENTIAL CIRCUITS USING GDI TECHNIQUE
GDI (Gate Diffusion Input) - A New Technique Of Low Power Digital Circuit Design Is Described. This Technique Allows Reducing Power Consumption, Delay And Area Of Digital Circuits, While Maintaining Low Complexity Of Logic Design. Performan...
COMPARISON AMONG LORA WAN AND OTHER LPWAN TECHNOLOGIES
The IoT (Internet Of Things) Requires The Expansion Of An Invisible, Intelligent Network That Can Be Controlled And Programmed. The Devices Used On This Network, Use The Embedded Technology, Which Allows Them To Communicate Either Directly...
SPLIT-RADIX FFT PROCESSORS USING RADIX-4 BUTTERFLY UNITS
For The Implementation Of Low-power FFT Processor, Split-radix Fast Fourier Transform (SRFFT) Is Widely Used. SRFFT Uses The Lowest Number Of Arithmetic Operations Amongst All The FFT Algorithms. Split-radix FFT Has The Same Signal Flow Gra...
1-BIT FULL ADDER BASED ON NOVEL SELF-CONTROLLABLE VOLTAGE LEVEL TECHNIQUE FOR LOW LEAKAGE CURRENT
In This Work Many Discharge Reduction Techniques Is Studied And Analyzed, Once That A Specific Discharge Reduction Technique Is Chosen. Hand-picked Technique Is Self-controllable Voltage Level (SVL) Technique. This Method Is Any Improved To...
OPTIMIZATION OF MEMRISTOR BASED SRAM CELL USING MTCMOS TECHNIQUE
Now A Day As The Technology Is Increasing Day By Day The Chip Size Is Decreasing And Millions Of Transistors Are Placed On A Single Chip As A Result The Design Complexity Is Increasing. Bottleneck Is To Reduce Some Parameters Related To Des...
RESEARCH REVIEW ON WIRELESS SENSOR NETWORKS
Wireless Sensor Network (WSN), The Surviving Group Built Moving Procedure May Affect In Bigger Network Workload. Some Of The Bunch Based Shared Trials Have Not Reduced Energy Swallowing And Re-transmissions That Stay Main Concerns Now WSN....
A NOVEL DESIGN OF RRAM BASED NONVOLATILE LOOKUP TABLE (NVLUT)
The Present Work Proposes A Novel Design Of RRAM Based Nonvolatile Lookup Table (nvLUT).Resistive Random Access Memory (RRAM) Is A Perfect Option To Replace Static Random Access Memory (SRAM) In Lookup Table (LUT) Design For Its High Densit...