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Papers tagged with "Power Dissipation"
VLSI IMPLIMENTATION OF FULL SUBTRACTOR USING SPLIT-RAIL CHARGE RECOVERY LOGIC
CMOS Technology Is Evolving Rapidly With The Advancement In VLSI Design. The Gate Count On The Integrated Chip Is Steadily Rising Which Leads To Enhanced Power Dissipation And Heat Generation. Therefore, A New Paradigm That Can Circumvent T...
SURVEY ON CLOUD COMPUTING: ENERGY SAVER
Energy Efficiency Is Increasingly Important For Future Information And Communication Technologies (ICT), Because The Increased Usage Of ICT, Together With Increasing Energy Costs And The Need To Reduce Greenhouse Gas Emissions Call...
IMPLEMENTATION OF TWO PHASE CLOCKED ADIABATIC STATIC CMOS LOGIC FULL ADDER DESIGN FOR EFFICIENT POWER DISSIPATION
An Efficient Power Dissipation With Adiabatic Logic Using 2 Phase Adiabatic Static CMOS Logic (2PASCL) Has Been Presented. In This Research Work Adiabatic Logic Is Mainly Used To Minimize The Energy Loss During The Operation Of The Circuit....
DESIGN OF 6T SRAM CELL AND RESULT ANALYSIS
Static Random Access Memory (SRAM) Is A Matrix Of Static Volatile Memory Cell. SRAM Has Become A Major Component In Many VLSI Chips Due To Their Large Storage Density And Small Access Time. SRAM Has Become Topic Of Substantial Research Due...