Design And Evaluation Of Low Power Decoder Circuit Using Viterbi Decoder

• Author(s):

  M.Gayathri | R.Jamuna

• Keywords:

  CMOS, Delay, Low Power, NAND, PDP, VLSI.

• Abstract:

  This Paper Presents A New Design Of A 2 To 4 Decoder Constructed Using 3-transistor NAND Gates, Contrasting It With The Conventional 4 Transistor NAND Gate-based Technique. The Primary Aim Of This Paper Is To Exhibit Advancements In Power Efficiency, Worst-case Propagation Time Delay, And Power Delay Product (PDP). These Improvements Underscore The Efficacy Of The 3-transistor NAND Gate-based Design, Illustrating Its Potential For Efficient And Optimized Decoder Architectures. The Simulation Of The Design Is Carried Out Using SPICE With 250nm Technology.

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Other Details

• Paper id:

  IJSARTV11I4102967

• Published in:

  Volume: 11 Issue: 4 April 2025

• Publication Date:

  2025-04-01

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