Volume 8, Issue 8 (August 2022)

Fault Tolerant Reversible Of Various Adders Design Using Different Low Power Consumption Techniques

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Author(s)

V.SahayaFathima Suja S.I.Padma S.M.Mustafa Nawaz

Abstract

GDI Technique Allows Minimization Of Area And Power Consumption Of Digital Circuits. The Reversible Gate Preserves Same Parity Between Output And Input Vectors Is Called Fault Tolerant But The Dimension Should Be 3. In This Design, Peres Gate Is Designed

Keywords

Peres Gate Reversible Logic Gate Low Power Gate Diffusion Input(GDI) Full Adder 120nm Technology Microwind 2 DSCH 2.

Paper ID

IJSARTV8I856717

Publication Date

August 16, 2022

Research Area

Communication Systems

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