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Papers tagged with "Clock"
DESIGN OF A 5-STAGE PIPELINED RISC-V PROCESSOR
This Paper Presents A Modified Design Of RISC-V RV32I 32-bit Microprocessor. The RISC-V Processor Consists Of A Flexible 5 Stage Pipelined Processor With Certain Techniques For Hazard Management. The Processor Consists Of 6 Blocks- Fetch Bl...
Clock As A Real-Life Example Of Group Theory
Group Theory Is One Of The Most Fundamental Branches Of Modern Algebra And Plays An Important Role In Various Areas Of Mathematics And Science. However, At The Undergraduate Level, It Is Often Perceived As A Highly Abstract Subject With Lit...
TIMING-ERROR-TOLERANT
The Timing Error Is Now Getting Increased Attention Because Of High Rate Of Error Occurrence On Semiconductor. In This Paper, The Clock Controlling System Is Used In Flip-flop To Prevent The Timing Error. Timing Error Would Be Detected And...
CHRONOPHARMACOLOGY: THE BIOLOGICAL CLOCK
Chronopharmacology Is The Science That Is Of Various Types In The Pharmacological Activities Of Various Treatment Over Organic Timings And Endogenous Balance. Chronopharmacology Is Useful For Solving Problems Of Drug Dosing Optimization, I....
DESIGN OF MULTIBIT FLIP-FLOP WITH ADAPTIVE CLOCK GATING FOR AREA EFFICIENT APPLICATIONS
Adaptive Clock-Gating (ACG) And Merging Flip-Flops In Which Several FFs Are Grouped And Share A Common Clock Driver Are Two Effective Low-power Design Techniques. Combining These Techniques Into A Single Grouping Algorithm And Design Flow E...
CLOCK SYNCHRONIZATION TECHNIQUE FOR WIRELESS SENSOR NETWORKS
The Wireless Sensor Networks Is The Type Of Network Which Is Used To Sense The Environmental Conditions Like Temperature, Pressure Etc. In This Work, Further Enhancement Will Be Proposed In RFID Protocol For Clock Synchronization. In The Pr...
ENHANCING FREQUENCY OF OPERATION OF A SINGLE CYCLE CPU USING FEW SYNTHESIS OPTIONS IN XILINX
A Clock Cycle Is Defined As The Time From One Rising Edge To The Next Rising Edge. A Synchronous Computer Is One In Which All Operations Are Controlled By A Clock. A Single-cycle CPU (central Processing Unit) Executes Each Instruction In One...
LOW POWER PULSE TRIGGERED D-FLIP FLOPS USING MTCMOS AND SELF CONTROLLABLE VOLTAGE LEVEL CIRCUIT
Reducing Power Consumption Is A Crucial Task For Any Circuits. Increased Demand For Portable Devices With Reduced Power Dissipation Has Put Necessary Traction To Design Low Power Circuits. Both Explicit And Implicit Pulse Triggered Flip Flo...
POWER REDUCTION USING PULSED LATCH METHOD IN LOOKAHEAD CLOCK GATING TECHNIQUE
Clock Gating Is One Of The Most Vital Techniques For Reducing Dynamic Power In The Sequential Circuits Where Presence Of Clock Signal At Undesired Instance Is A Major Problem. The Major Power Consuming Components In Electronics Product Is T...
DESIGN OF MODIFIED DATA DRIVEN CLOCK GATING AND LOOK AHEAD CLOCK GATING FOR LOW POWER
Clock Signal Is Considered As An Immense Source Of Power Dissipation In Synchronous Circuits Because Of Large Frequency And Load. It Does Not Carry Any Information But Consumes High Power At The Switching Activity Which Is To Be Avoided. So...
POWER REDUCTION TECHNIQUES IN VLSI USING 8X10 ENCODER & 10X8 DECODER WITHOUT RIPPLE COUNTER
In Today’s Time The VLSI Industry Is Growing Rapidly And It Demands For The Devices Which Consume Less Power And There Is No Impact On Their Performance. Maintaining The Performance With Less Power Consumption Is The Big Task For The Engine...
COMPUTER SIMULATED & MATHEMATICAL MODELING FOR MECHANICAL TIMER BY USING RUNWAY ESCAPEMENT MECHANISM
Aim Of This Paper Is To Develop Realistic And Workable Computer Program To Simulate Dynamic Behavior Of The Runaway Escapement. A Theoretical Analysis Was Conducted And The Mathematical Model Of The Motion Of Mechanical Timer Device Con...