Design And Physical Implementation Of An Int8 Output-stationary Systolic Array Cnn Accelerator For Tinyml Inference Using Open-source Sky130 Pdk And Openlane Eda Flow

Abstract

This Paper Presents The Design And Complete Physical Implementation Of A 4×4 INT8 Output-stationary Systolic Array Accelerator For TinyML Convolutional Neural Network (CNN) Inference, Targeting Edge Vision Applications Such As Image Classification And Object Detection On Resource-constrained Devices. The Proposed Architecture Addresses The Fundamental Energy Inefficiency Of General-purpose Processors Executing Fixed Computational Workloads. The Accelerator Was Designed In Verilog HDL Comprising Seven Modules Including MAC Units, Processing Elements, 4×4 Systolic Array Fabric, On-chip Input And Output Data Buffers, And A Finite State Machine Controller And Physically Implemented Using The Open-source OpenLane RTL-to-GDSII EDA Flow Targeting The SkyWater SKY130 130nm/180nm Hybrid Process Design Kit. Two Complete Implementation Runs Achieved Zero Design Rule Check (DRC) Violations. The Complete Buffered System Achieves A Post-route Critical Path Delay Of 3.07 Ns, Enabling Operation Up To 325 MHz, With 23.3 µW Total Power At The Typical Process Corner (TT, 1.8V, 25°C). Functional Correctness Was Verified Using A Sobel-X Edge Detection Conv2D Kernel With Outputs Confirmed Identical Between RTL Simulation And ESP32-WROOM-DA Hardware. Power Comparison Against ESP32 At 347.43 MW Demonstrates A 14,911× Total Power Reduction And 477,187× Better Energy Per Conv2D Operation.

Keywords