Fault-tolerant Reversible-logic Based Ro-puf For Secure Device Authentication

• Author(s):

  S.Gayathri | P.Sridevi

• Keywords:

  Reversible Logic, Double-Feynman Gate, Fault-tolerant Gates.

• Abstract:

  Protecting Data And Hardware Is Vital, Drivingthe Adoption Of Physically Unclonable Functions (PUFs) For Generating Unique Circuit Signatures. This Paper Introduces A Fault-tolerant System Featuring A Ring-oscillator (RO) Based PUF, Utilizing A Reversible Logic (RL) Design. The Proposed System Comprises Various Sub-systems Such As Fault-Tolerant RL-based Inverter Design, Reversible-Logic Designing, Fault-Detection Module, Fault-free Path Selection Module, And The Reversible RO-PUF Module. The Proposed Design Is Implemented On A Basys-3 FPGA Board For Calculating Various PUF Parameters. It Is Observed That The Uniqueness, Uniformity, And Bit-aliasing Of The Proposed Design At 27◦C Are 49.40%, 51.20%, And 48.30%, Respectively. Further, Bit-error-rate (BER), Reliability, And Key Error Rate (KER) Are Determined At Three Different Temperatures, And The Best Results Obtained Are 0.003%, 99.7%, And 0.092 At 40◦C, Respectively. Compared To Conventional PUFs, The Proposed Design Showcases Higher Reliability (0.002% To 0.11%) And Significantly Reduced BER And KER (1.67× To 22.67×, And 1.6× To 8.02× Respectively). The Proposed Design Also Passed 15 NIST Tests Against Conventional RO-PUF, Which Could Pass Only 11 NIST Tests. We Have Also Tested The Resilience Of Different PUF Designs Against Three Machine-learning Models With The Best Accuracy Of 58.9% Against The Logistic Regression Model.

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Other Details

• Paper id:

  IJSARTV11I4103409

• Published in:

  Volume: 11 Issue: 4 April 2025

• Publication Date:

  2025-04-30

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