Design Of Uart-transmitter Using Fsm In Verilog Hdl

• Author(s):

  Ahalya S | Alagulakshmi P | Jayasri P | Maha lakshmi S | Dr.R.Sudha

• Keywords:

  UART, Finite State Machine (FSM), Verilog HDL, Serial Communication, Parallel-to-Serial Conversion, Digital Design, Data Transmission.

• Abstract:

  This Project Presents The Design And Implementation Of A UART (Universal Asynchronous Receiver/Transmitter) Transmitter Using A Finite State Machine (FSM) In Verilog HDL. UART Is A Widely Used Serial Communication Protocol That Enables Data Transfer Between Devices Without The Need For A Shared Clock Signal. The Proposed System Converts Parallel Input Data Into A Serial Data Stream By Following The Standard UART Frame Format, Which Includes A Start Bit, Data Bits, And A Stop Bit.The Design Utilizes An FSM To Control The Sequential Transmission Process Through Different States Such As IDLE, START, DATA, And STOP. A Shift Register And Bit Counter Are Used To Ensure Correct Data Sequencing And Timing. The Implementation Is Verified Using A Testbench And Simulated To Observe Correct Waveform Behavior.This Project Provides A Simple And Efficient Approach For Implementing UART Communication In Digital Systems And Can Be Extended To Include Features Such As Parity Checking, Baud Rate Generation, And Full-duplex Communication For Real-time Embedded Applications.

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Other Details

• Paper id:

  IJSARTV12I5105259

• Published in:

  Volume: 12 Issue: 5 May 2026

• Publication Date:

  2026-05-04

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