Design And Fpga Implementation Of A Secure Uart Architecture Integrating Aes-128 Encryption And Secded Error Correction

Abstract

This Paper Presents An FPGA-oriented Secure UART Architecture Combining AES-128 Confidentiality With SECDED Protection Against Transmission Faults. Sixteen 8-bit Plaintext Bytes Are Buffered Into A 128-bit AES Block, Encrypted, And Protected Before Serial Transfer; At The Receiver, The Protected Data Are Checked, Corrected Where Possible, Reconstructed, And Decrypted. The Design Is Implemented In Verilog HDL And Verified Through RTL Simulation And Post-synthesis FPGA Analysis, Covering The FIPS-197 AES-128 Known-answer Test, UART Transmission/reception, Single-bit Correction, Double-bit Detection, And An End-to-end Encrypted Round Trip. Post-synthesis Reports Quantify FPGA Resource Utilization; Timing, Power, Latency, And Throughput Require Clock, I/O, And Switching-activity Constraints Not Yet Applied.

Keywords