Volume 5, Issue 3 (March 2019)

Delay And Power Analysis Of Various Flip Flop Using Spartan 3e Fpga Kit

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Author(s)

K.Rajesh M.Shenbagapriya R.Hemalatha G.Neelavathi

Abstract

The Flip-flop Has Two States Which Are Shown In The Below Figure. When Q=1; And Q’=0; It Is In The Set State . When Q=0 & Q’=1, It Is In The Clear State . The Outputs Of The Flip Flop Q & Q’ Are Complements Of Each Other And Are Referred To As The Normal


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Paper ID

IJSARTV5I329560

Publication Date

March 12, 2019

Research Area

ECE

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