HIGH SPEED PACKET CLASSIFICATION USING FPGA

Performing Packet classification effectively in network infrastructure is becoming a major challenge because of demand in increasing throughput and speed of enhancement. Many previous techniques which are used for packet classification focused on throughput only and they cannot reduce the searching speed. So a dynamically updatable packet classification along with parity generator is proposed to enhance the speed of searching by reducing the number of comparison operations. A special hardware support is an attractive alternative to enhance the speed of operation. The time required for classifying a packet in network infrastructure is reduced greatly. This technique enhances the searching speed and also reduces the propagation delay.