design of low-power high-gain serializer/deserializer using gdi technique

CMOS technology is evolving Propose and demonstrate a serializer/deserializer (SerDes) toward the testing of large scale GDI circuits with delay-line clocking. A SerDes, a pair of a serializer (parallel-to-serial converter) and a deserializer (serial-to-parallel converter), is an important circuit block in cryogenic experiments. For instance, the number of available Input/Output (I/O) cables is limited by equipment such as a cryostat and cryoprobe, so that it is crucial to reduce the number of I/O cables as much as possible using a Ser/Des, especially when testing a large scale superconductor circuit. In RSFQ logic, serializers and deserializers are implemented by shift registers, which store data during Serial-to-Parallel (S2P) and Parallel-to-Serial (P2S) conversion. As for GDI logic, we previously proposed and demonstrated the feedback type SerDes , where an GDI buffer chain with feedback paths operates in a similar way to a shift register. However, this Ser/Des was developed for four-phase clocking and does not operate in delay-line clocking, because feedback paths are difficult to make in delay-line clocking due to the low latency. Therefore, we develop a novel SerDes for testing delay-line-clocked GDI circuits by combining GDI and RSFQ technologies, which we refer to as the GDI hybrid SerDes.