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FPGA Implementation of I2C and SPI Protocols using VHDL


Satish M Ghuse


Xilinx Software 14.5, Model Sim Software, I2C Serial communication Protocol, SPI Serial Communication Protocol, Pipelined Buffer


I2C and SPI are the serial communication protocols that are commonly used for both intra-chip and inter-chip low/medium bandwidth data transfer. It can support bidirectional data transfers at up to 100 Kbit/s in the standardmode, up to 400 Kbit/s in the Fast-mode, up to 1 M bit/s in the Fast-mode plus, or up to 3.4 M bit/s in the High-speed mode. These protocols have a preferable speed and power consumption capability when implemented with different devices but their speed is low, when used with BIST or checksums. In the earlier systems speed and delay was not taken into the consideration and the protocol was implemented as it is in the standard mode. We are about to implement the I2C and SPI protocols efficiently so that the speed of the data transfer increases and there delay is reduced. In order to do so we have proposed a design in which we are using pipelined buffer in between Master and Slave so that it will reduce the delay and there would be synchronization and increase in the speed of data transfer as the delay in data transfer decreases. The pipelined buffer results in the speed enhancement for the critical paths. Using this pipelined buffer the data transferred from master is first stored in buffer and then transferred to the slave and vice-versa. The delay is in the form of nanoseconds in which when used pipelined buffer in the system route delay is neglected and only logic delay is considered. The speed is calculated using the delay of the system in the form of Mbps or Gbps depending on the delay. The delay report for both the protocols are taken from synthesis report generated in the Xilinx software and the simulation of the system is done in the model-sim software.

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Published in: Volume : 2, Issue : 10
Publication Date: 10/1/2016

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