SCHMITT TRIGGER BASED 4T SRAM CELL

Due to wide-spread use of electronic devices, embedded memories play a significant role in modern era. Due to fast and random access, SRAM is mainly used as a cache memory. But in low power VLSI, Stability degrades due to technology scaling and fluctuations in process parameters that is oxide thickness, diffusion depth and density of impurity concentration etc. Thus to measure stability, static noise margin is the main performance parameter in SRAM cell. This paper presesnts SRAM topologies, conventional 4t and Schmitt Trigger based SRAM bit cell. These two topologies are characterized and compared on the basis of their Read and Write SNM with dynamic power supply.