LOW COMPLEXITY AND POWER EFFICIENT ASYNCHRONOUS DESIGN BASED ON NCL LOGIC

NULL convention logic (NCL) is a promising design paradigm for constructing low-power robust asynchronous circuits.NCL has been employed for a variety of applications, including low-power circuit design, fault-attack-resistant cryptographic circuits, ternary logic, and robust circuit design for operating in space environment The conventional NCL paradigm requires pipeline registers for separating two neighboring logic blocks, and those registers can account for up to 35% of the overall power consumption of the NCL circuit. This brief presents the register-less NULL convention logic (RL-NCL) design paradigm, which achieves low power consumption by eliminating pipeline registers, simplifying the control circuit, and supporting fine-grain power gating to mitigate the leakage power of sleeping logic blocks. Further, to improve dual-rail complexity and to achieve high-throughput pipeline design method, targeting to latch-free and extremely fine-grain is constructed. The data paths are composed of a mixture of dual-rail and single-rail gates. Dual-rail gates are limited to construct a stable critical data path. Compared with the conventional NCL counterpart, the Hybrid–Rail RL-NCL implementation of an eight-bit five-stage pipelined Kogge-Stone adder can reduce power dissipation for the input data rate ranging from 10 MHz to 900 MHz. Moreover, the Hybrid–Rail RL-NCL implementation can reduce the transistor count of the adder which results in optimized area compared to RL-NCL Kogge-Stone adder.