VARIABILITY AWARE DESIGN OF FULL ADDER

• Author(s):

  C Rajendra Prasad | Mr. M Mahaboob Basha | S Bala Mohan

• Keywords:

• Abstract:

  Under Ultra-deep Sub-micron Technology Node As There Is Continues Reduction In The Feature Size To Few Nanometers Will Results Adverse Effect Of Process, Voltage And Temperature (PVT) Variations On Design Metrics Of Circuit. Hence It Is Proposed That How

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Other Details

• Paper id:

  IJSARTV10I693223

• Published in:

  Volume: 10 Issue: 6 June 2024

• Publication Date:

  2024-06-09

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