SRAM SIZE AND POWER DISSIPATION REDUCTION BY USING 4 STORAGE CELLS & 1 ACCESS TRANSISTOR

• Author(s):

  Supriya Raj | Vishal Shrivastava

• Keywords:

  DSCH2, Microwind, SRAM, DRC.

• Abstract:

  This Paper Gives The Concept Of Using 5 Transistors SRAM So That It Can Be Utilized In The Place Of 6 Transistors SRAM. By Using DSCH2 And Microwind 2.6K I Have Design Layout Of 5T SRAM In 2.5µm And 1.5µm Technology And Perform Read And Write Operation. B

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Other Details

• Paper id:

  IJSARTV5I1033309

• Published in:

  Volume: 5 Issue: 10 October 2019

• Publication Date:

  2019-10-03

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