Shift Register Design Using Pulse Triggered Flipflop

• Author(s):

  Nandhini | E. Vimal

• Keywords:

  Pulse Triggered Flip Flop Design, Microwind, Dsch2,VLSI

• Abstract:

  The Timing Elements And Clock Interconnection Networks Such As Flip-flops And Latches, Is One Of The Most Power Consuming Components In Modern Very Large Scale Integration (VLSI) System. The Area, Power And Transistor Count Will Compared And Designed

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Other Details

• Paper id:

  IJSARTV2I63550

• Published in:

  Volume: 2 Issue: 6 June 2016

• Publication Date:

  2016-06-18

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