POWER REDUCTION USING PULSED LATCH METHOD IN LOOKAHEAD CLOCK GATING TECHNIQUE

• Author(s):

  Tamil Chindhu S | Dr.N.Shanmugasundaram

• Keywords:

  Dynamic Power, Clock Gating, Cell, Latch, Flip-flop, LACG, Data Driven, Auto Gated Flipflop, Low Power Consumption, Sequential Circuits.

• Abstract:

  Clock Gating Is One Of The Most Vital Techniques For Reducing Dynamic Power In The Sequential Circuits Where Presence Of Clock Signal At Undesired Instance Is A Major Problem. The Major Power Consuming Components In Electronics Product Is The Systems Cloc

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Other Details

• Paper id:

  IJSARTV4I523739

• Published in:

  Volume: 4 Issue: 5 May 2018

• Publication Date:

  2018-05-29

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