IMPLEMENTATION OF TWO PHASE CLOCKED ADIABATIC STATIC CMOS LOGIC FULL ADDER DESIGN FOR EFFICIENT POWER DISSIPATION

• Author(s):

  Dr.C.Venkatesh | A.Mohanapriya

• Keywords:

  Adiabatic Logic, Energy Recovery, Full Adder, Power Dissipation, 2PASCL

• Abstract:

  An Efficient Power Dissipation With Adiabatic Logic Using 2 Phase Adiabatic Static CMOS Logic (2PASCL) Has Been Presented. In This Research Work Adiabatic Logic Is Mainly Used To Minimize The Energy Loss During The Operation Of The Circuit. The Adiabatic

---

Other Details

• Paper id:

  IJSARTV4I523741

• Published in:

  Volume: 4 Issue: 5 May 2018

• Publication Date:

  2018-05-29

Download Article