Impact Factor
7.883
Call For Paper
Volume 10 Issue 12 December 2024
LICENSE
IMPLEMENTATION OF 2-BIT AND 4-BIT MAGNITUDE COMPARATOR USING FULLER ADDER
-
Author(s):
Raman Shrivastava | Prof.Shweta Agrawal
-
Keywords:
Full Adder, VLSI, Low Power, Magnitude Comparator.
-
Abstract:
In Today’s Era, The Digital VLSI Circuit Should Have Low Power, High Speed And Small In Size, These Parameters Plays Very Important Role In VLSI Designing. In This Paper We Present A New Technique To Implement 2-bit Magnitude Comparator And 4-bit Magnitud
Other Details
-
Paper id:
IJSARTV4I423200
-
Published in:
Volume: 4 Issue: 4 April 2018
-
Publication Date:
2018-04-29
Download Article