Implementation Of 2-bit And 4-bit Magnitude Comparator Using Fuller Adder

• Author(s):

  Raman Shrivastava | Prof.Shweta Agrawal

• Keywords:

  Full Adder, VLSI, Low Power, Magnitude Comparator.

• Abstract:

  In Today’s Era, The Digital VLSI Circuit Should Have Low Power, High Speed And Small In Size, These Parameters Plays Very Important Role In VLSI Designing. In This Paper We Present A New Technique To Implement 2-bit Magnitude Comparator And 4-bit Magnitud

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Other Details

• Paper id:

  IJSARTV4I423200

• Published in:

  Volume: 4 Issue: 4 April 2018

• Publication Date:

  2018-04-29

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