FAULT TOLERANT REVERSIBLE OF VARIOUS ADDERS DESIGN USING DIFFERENT LOW POWER CONSUMPTION TECHNIQUES

• Author(s):

  V.SahayaFathima Suja | S.I.Padma | S.M.Mustafa Nawaz

• Keywords:

  Peres Gate, Reversible Logic Gate, Low Power, Gate Diffusion Input(GDI), Full Adder, 120nm Technology, Microwind 2, DSCH 2.

• Abstract:

  GDI Technique Allows Minimization Of Area And Power Consumption Of Digital Circuits. The Reversible Gate Preserves Same Parity Between Output And Input Vectors Is Called Fault Tolerant But The Dimension Should Be 3. In This Design, Peres Gate Is Designed

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Other Details

• Paper id:

  IJSARTV8I856717

• Published in:

  Volume: 8 Issue: 8 August 2022

• Publication Date:

  2022-08-16

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