DIGITAL PHASE LOCKED LOOP: AN FPGA IMPLEMENTATION

• Author(s):

  Divya rajan

• Keywords:

  Phase Detector, Loop Filter, DCO, FPGA

• Abstract:

  A PLL Is A Negative Feedback System Where An Oscillator Generated Signal Is Phase And Frequency Locked To A Reference Signal. To Overcome The Drawbacks Of The Conventional PLL, The Analog PLL Is Modified Using All Digital Components. In This Paper, ADPLL

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Other Details

• Paper id:

  IJSARTV4I523326

• Published in:

  Volume: 4 Issue: 5 May 2018

• Publication Date:

  2018-05-04

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