DESIGN-SPECIFIC PATH DELAY TESTING IN LOOKUP-TABLE-BASED FPGAS

• Author(s):

  S. Sulochana

• Keywords:

• Abstract:

  Due To The Increased Use Of Field Programmable Gate Arrays (FPGAs) In Production Circuits With High Reliability Requirements, The Design-specific Testing Of FPGAs Has Become An Important Topic For Research. Path Delay Testing Of FPGAs Is Especially Import

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Other Details

• Paper id:

  IJSARTV5I329607

• Published in:

  Volume: 5 Issue: 3 March 2019

• Publication Date:

  2019-03-15

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