DESIGN OF MULTIBIT FLIP-FLOP WITH ADAPTIVE CLOCK GATING FOR AREA EFFICIENT APPLICATIONS

• Author(s):

  M. Sreenivasula Reddy | B. Umakanth

• Keywords:

  Clock Gating (CG), Clock Network Synthesis, Low-power Design, Pass Transistor Logic.

• Abstract:

  Adaptive Clock-Gating (ACG) And Merging Flip-Flops In Which Several FFs Are Grouped And Share A Common Clock Driver Are Two Effective Low-power Design Techniques. Combining These Techniques Into A Single Grouping Algorithm And Design Flow Enables Further

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Other Details

• Paper id:

  IJSARTV6I839378

• Published in:

  Volume: 6 Issue: 8 August 2020

• Publication Date:

  2020-08-28

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