High Impact Factor : 7.883
Submit your paper here

Impact Factor

7.883


Call For Paper

Volume 10 Issue 12 December 2024


Download Paper Format


Copyright Form


Share on

DELAY AND POWER ANALYSIS OF VARIOUS FLIP FLOP USING SPARTAN 3E FPGA KIT

  • Author(s):

    K.Rajesh | M.Shenbagapriya | R.Hemalatha | G.Neelavathi

  • Keywords:

    FPGA(Field Programmable Gate Array),

  • Abstract:

    The Flip-flop Has Two States Which Are Shown In The Below Figure. When Q=1; And Q’=0; It Is In The Set State . When Q=0 & Q’=1, It Is In The Clear State . The Outputs Of The Flip Flop Q & Q’ Are Complements Of Each Other And Are Referred To As The Normal

Other Details

  • Paper id:

    IJSARTV5I329560

  • Published in:

    Volume: 5 Issue: 3 March 2019

  • Publication Date:

    2019-03-12


Download Article