CMOS ASIC DESIGN AND IMPLEMENTATION OF PHASE LOCKED LOOP USING CADENCE EDA TOOL

• Author(s):

  M.Sangeetha | R.Jeevitha | C.Nandhini | B.N.Muralidaran

• Keywords:

  Charge Pump, Loop Filter, Phase Frequency Detector, Voltage Control Oscillator.

• Abstract:

  Phase Locked Loop Is The Heart Of The Many Modern Electronics As Well Communication System. Hence There Is Necessity Of A PLL Which Must Operate In The GHz Frequency Range. PLL Is A Mixed Signal Circuit As Its Architecture Involves Both Digital And Analog

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Other Details

• Paper id:

  IJSARTV4I321792

• Published in:

  Volume: 4 Issue: 3 March 2018

• Publication Date:

  2018-03-23

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