AREA AND DELAY EFFICIENT VEDIC MULTIPLIER USING PIPELINE TECHNIQUE

• Author(s):

  Deepak Mittal | Prof. Sunil Shukla

• Keywords:

  FPGA, Pipeline Technique, U-T Sutra, Vedic Mathematics, Vedic Multiplier

• Abstract:

  This Paper Describes The Design And Implementation Of Area And Delay Efficient Vedic Multiplier Using Pipeline Technique. The Hardware Kit Utilized For Implementation Is Altera FPGA Model No. EP3C16F484C6 At 65 Nm Technology At 1.2 V. The Implementati

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Other Details

• Paper id:

  IJSARTV2I42081

• Published in:

  Volume: 2 Issue: 4 April 2016

• Publication Date:

  2016-04-06

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