ANALYSING THE PERFORMANCE OF LOW POWER HIGH SPEED FULL ADDERS USING STRAINED SILICON CMOS TECHNOLOGY

• Author(s):

  Dr.T.Ravichandran | S.Naveena | S.Monishraj | M.Ramkumar

• Keywords:

  Delay, Full-adder (FA), Power Consumption.

• Abstract:

  In Most Of The Digital Circuits, Communication Systems And Digital Signal Processing, Adders Play A Major Role Since They Are The Basic Blocks. In This Paper, The Performance Of Full-adder (FA) Circuits Has Been Studied. The Full Adder Circuits Were Desig

---

Other Details

• Paper id:

  IJSARTV5I329862

• Published in:

  Volume: 5 Issue: 3 March 2019

• Publication Date:

  2019-03-28

Download Article