A Novel 4-bit Full Adder Design For Power And Area Optimization

• Author(s):

  Mr. Snehal Kumbhalkar | Mr. Sanjay Tembhurne

• Keywords:

  Gate Diffusion Input, Full Adder, Half Adder

• Abstract:

  In The Modern Era, Power Dissipation And Area Of The Circuit Under Fabrication Has Become A Major And Vital Constraint In The Electronic Industry. The Objective Of This Paper Is To Reduce The Power Dissipation In The Circuit By Using Gate Diffusion In

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Other Details

• Paper id:

  IJSARTV2I31862

• Published in:

  Volume: 2 Issue: 3 March 2016

• Publication Date:

  2016-03-15

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