LOW PDP CMOS FULL ADDER DESIGN

In this work efforts are made to improve the performance of full adder with re-spect to power-delay product, power dissipation and time delays using 90nm CMOS technology. Currently there are two techniques used namely alternative internal logic structure and pass-transistor logic style that gives reduced power-delay product (PDP). We implement the full adder using above mentioned technologies and try to compare their performance and further develop a technology which will give the low PDP and low power consumption.