LOW PDP CMOS FULL ADDER DESIGN |
Author(s): |
Ms. Chaitali L Landge |
Keywords: |
PDP,CMOS |
Abstract |
In this work efforts are made to improve the performance of full adder with re-spect to power-delay product, power dissipation and time delays using 90nm CMOS technology. Currently there are two techniques used namely alternative internal logic structure and pass-transistor logic style that gives reduced power-delay product (PDP). We implement the full adder using above mentioned technologies and try to compare their performance and further develop a technology which will give the low PDP and low power consumption. |
Other Details |
Paper ID: IJSARTV Published in: Volume : 2, Issue : 12 Publication Date: 12/14/2016 |
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