Simultaneous Reduction Of Dynamic And Static Power In Scan Mode (CMOS Technology) Using C-Algorithm

• Author(s):

  Ms. J.suganya | Ms.S.Sudha

• Keywords:

• Abstract:

  Power Dissipation During Test Is A Major Challenge In Testing Integrated Circuits. Dynamic Power Has Been The Dominant Part Of Power Dissipation In CMOS Circuits, However, In Future Technologies The Static Portion Of Power Dissipation Will Outreach T

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Other Details

• Paper id:

  IJSARTV1I11

• Published in:

  Volume: 1 Issue: 1 January 2015

• Publication Date:

  2015-01-13

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