REVIEW ON OPTIMIZED ROUTER PIPELINE STAGES USED FOR NETWORK ON CHIP

• Author(s):

  Yudhishtir U. Bhangale | Prof. Neetesh Raghuwanshi | Prof. Jayant P. Bhoge

• Keywords:

  Network-on-chip, XY Routing Algorithm, Field Programmable Gate Array(FPGA), VHDL, System-on-chip (SoC), Latency.

• Abstract:

  As The Feature Size Is Continuously Decreasing And Integration Density Is Increasing, Interconnections Have Become A Dominating Factor In Determining The Overall Quality Of A Chip. Due To The Limited Scalability Of System Bus, It Cannot Meet The Requireme

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Other Details

• Paper id:

  IJSARTV3I1117938

• Published in:

  Volume: 3 Issue: 11 November 2017

• Publication Date:

  2017-11-15

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