REDUCE AREA & WIRE LENGTH MODULE DESIGN OF 256 X 16 NON- VOLATILE RAM BASED ON FM25H20 FRAM

• Author(s):

  Yashoda Kumari | Dr. R.K. Dubey

• Keywords:

  VHDL, XILLINX, RAM, C-RAM, M-RAM, TWB, SBO

• Abstract:

  This Paper Describes A Design Methodology Of A 256 × 16 RAM Using VHDL To Ease The Description, Verification, Simulation And Hardware Realization. A 256 × 16 RAM Has 16-bit Data Length. This Can Read And Write 16-bit Data. Vectorizing Involves Parallel A

---

Other Details

• Paper id:

  IJSARTV4I523692

• Published in:

  Volume: 4 Issue: 5 May 2018

• Publication Date:

  2018-05-27

Download Article