FPGA Implementation Of Multiply-Add Unit Based On 2^(n+1) Modulo Arithmetic

• Author(s):

  E. Jebamalar Leavline | N. Renukadevi | R. Sivapriyanka, G. Santhiya

• Keywords:

• Abstract:

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Other Details

• Paper id:

  IJSARTV1I10472

• Published in:

  Volume: 1 Issue: 10 October 2015

• Publication Date:

  2015-10-25

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