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title

DESIGN OF 64-BIT ARITHMETIC LOGIC UNIT (ALU) BASED ON BSIM4 MODEL USING TANNER

Author(s):

Pragati Nagdeote

Keywords:

Arithmetic logic unit, adiabatic logic, CMOS technology, Tanner tool EDA

Abstract

Arithmetic circuits play a vital role in computational and digital circuits. Arithmetic Logic Unit (ALU) can perform various arithmetic and logical functions. Proposed 64-bit ALU comprises of different arithmetic functions such as addition, subtraction and logical functions like AND logic, OR logic, NOR logic and NAND logic. ALU always faces the issues of power consumption when there are the complex operations, therefore to overcome this problem the low power 64-bit ALU is designed using adiabatic logic with 180nm CMOS technology. BSIM4 model is used for the implementation of 64-bit full adder, 64-bit AND logic, 64-bit OR logic, 4:1 Multiplexer, 2:1 Multiplexer and Proposed design is verified using tanner EDA (V-13.0) tool. Parametric analysis of 64-bit ALU is done. Proposed Arithmetic Logic Unit is proved to be efficient in terms of Area, Power and Delay.

Other Details

Paper ID: IJSARTV
Published in: Volume : 2, Issue : 10
Publication Date: 10/1/2016

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