EFFICACIOUS CONVOLUTION AND DECONVOLUTION VLSI ARCHITECTURE FOR PRODUCTIVENESS DSP APPLICATIONS

Current scenario in mobile Communication and multimedia applications require high-performance and lowpower VLSI signal processing (DSP) systems. Most broadly used operations in DSP are FIR and IIR filter. The convolution and deconvolution with a very lengthy sequence is everywhere in wide area of application in Digital Signal Processing. Convolution used to compute the output of a system with arbitrary input, with information of impulse response of the system. Primary constriction of any application to work fast is that boost the speed of their basic building block. Both operations consume much of time. More number of techniques is developed to improve the speed of the Multiplier and Divider, The Vedic Multiplier and Divider technique is more considerable and satisfied all the constraints. Because, of faster working and low power consumption. The most considerable aspect of the proposed method is the growth of a multiplier and divider architecture based on Ancient Indian Vedic Mathematics sutras Urdhvatriyagbhyam and Nikhilam algorithm. In this paper the time delay of Convolution and Deconvolution is improved using Vedic multiplier and Divider. We proposed to design of linear convolution and circular convolution using Vedic mathematics is functionally verified and simulated using Modelsim software and implemented on Spartan 3E FPGA kit using Xilinx software, parameter like area, speed and power will be compared to their implementation using conventional multiplier & divider architectures.