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Volume 5 Issue 10

October 2019

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title

SRAM SIZE AND POWER DISSIPATION REDUCTION BY USING 4 STORAGE CELLS & 1 ACCESS TRANSISTOR

Author(s):

Supriya Raj

Keywords:

DSCH2, Microwind, SRAM, DRC.

Abstract

This paper gives the concept of using 5 Transistors SRAM so that it can be utilized in the place of 6 Transistors SRAM. By using DSCH2 and Microwind 2.6K I have design layout of 5T SRAM in 2.5µm and 1.5µm technology and perform read and write operation. By using Microwind 2.6K software, we can design a layout diagram and checked by using a DRC rule checker and after that simulate the layout and do the analysis. It helps to decrease the memory size.

Other Details

Paper ID: IJSARTV
Published in: Volume : 5, Issue : 10
Publication Date: 10/3/2019

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