CONVOLUTION USING URDHVA TIRYAGBHYAM

Multiplication is fundamental operation of most of the signal processing systems. Convolution process needs multiplication. To speed up convolution process at very appreciable extent. Multiplier used needs to be speedy. Here Direct method of computing the discrete linear convolution of finite length sequences is used. 4×4 bit Vedic multipliers based on Urdhva Tiryagbhyam sutra also called as “Vertically and cross wise.” are used. Here two different approaches of convolution are compared. For Serial circuit it gives saving in area occupied while for parallel approach, it gives speed improvement when implemented on 90 nm process technology FPGA. It also provides necessary modularity, expandability, and regularity to form different convolutions for any number of bits. The coding is done in VHDL (Very High Speed Integrated Circuits Hardware Description Language) for the FPGA , as it is being increasingly used for variety of computationally intensive applications.