DESIGN OF FAST AND LOW COMPLEXITY FAULT TOLERANT FFTS USING PARSEVAL CHECK

In most of the recent processors , multimode memory unit is used which needs digital filters to avoid unwanted faults in the process components and in some cases, the reliability of those systems is critical, and fault tolerant filter implementations are needed. A soft error is an issue that causes a temporary condition in RAM that alters stored data in the FFT. First method, the Parity-Partial Summation and Error Correction Codes (ECC) uses one FFT with minimum Partial Sum blocks for reducing hardware area. Parallel Partial Summation ECC used for correcting errors in multiple FFTs protective methods. The result for 4-paralle1 FFTs shows that the proposed technique effectively reduces delay of fault tolerant design by detecting and correcting the multiple errors at a time. The existing methods used the methods to detect and correct the single error in FFT. We have proposed partial summation method to detect and correct multiple errors simultaneously. The result for proposed method shows that it effectively reduces the timing process in detecting and correcting the errors in FFT.